library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity I2CpacketGen is
end I2CpacketGen;

architecture behav of I2CpacketGen is

  signal i2cClk : std_logic:='0';
  signal i2cData : std_logic:='1';
  
  signal address : std_logic_vector(7 downto 0):="10011001";
  signal reg : std_logic_vector(7 downto 0):="10101010";
  signal data : std_logic_vector(7 downto 0):="11001100";
  
  component I2Cwatcher is
  Port(I2CData : in std_logic;
       I2CClk : in std_logic;
       Direction : out std_logic);
  end component;
  
  signal dir : std_logic;

begin
  
  i2cClk<= not i2cClk after 20 ns;
  
  UUT: I2Cwatcher port map(i2cData,i2cClk,dir);
  
  process
  begin
    --wait for bootup
    wait for 120 ns;
    --send start bit
    wait for 30 ns;
    i2cData<='0';
    wait for 10 ns;
    i2cData<='1';
    --send address
    for i in 7 downto 0 loop
      wait for 15 ns;
      i2cData<=address(i);
      wait for 25 ns;
    end loop;
    i2cData<='1';
    --send ack
    wait for 15 ns;
    i2cData<='0';
    wait for 25 ns;
    i2cData<='1';
    --send regID
    for i in 7 downto 0 loop
      wait for 15 ns;
      i2cData<=reg(i);
      wait for 25 ns;
    end loop;
    i2cData<='1';
    --send ack
    wait for 15 ns;
    i2cData<='0';
    wait for 25 ns;
    i2cData<='1';
    --send data
    for i in 7 downto 0 loop
      wait for 15 ns;
      i2cData<=data(i);
      wait for 25 ns;
    end loop;
    i2cData<='1';
    --send ack
    wait for 15 ns;
    i2cData<='0';
    wait for 25 ns;
    i2cData<='1';
     --send stop bit
    i2cData<='0';
    wait for 30 ns;
    i2cData<='1';
    wait for 10 ns;
    
    
    ----------------------
    wait;
  end process;
  
end behav;